Data processing systems with two or more processing units are known. For example, U.S. Pat. No. 6,615,366 discloses a processor with dual execution cores that may be switched dynamically between high reliability and high performance execution modes. When the processor is in high reliability mode, the dual execution cores operate in lock step on identical instructions. In the high performance mode the dual execution cores operate independently.
However, a disadvantage of this prior art processor is that, in the high performance mode, the performance of the processor is limited because the executions cores cannot share resources. Accordingly, for example when an execution core performs an operation with a high processing load in the high performance mode, and the other execution core performs an operation with a low processing load in the high performance mode, resources of the latter are underutilised.
United States Patent Application publication US 2006/0161918 discloses a microprocessor system with safety functions. The system includes a plurality of processor cores. Each of the cores is connected to peripheral elements by way of its own, separate, bus. In case of a safety critical algorithm running on the microprocessor system, the cores and the peripheral elements operate as a fully redundant system using fully redundant memory addresses in the respective peripheral memory elements. A bridging device is present which can be used to transmit bus information from one bus to the other bus and to have an address monitoring device connected to the bridging device store information in a non-redundant memory address in case of a non-safety critical algorithm running on the processor core.
However, a disadvantage of this microprocessor system is that although additional resources are available in case the processor core runs a non-safety critical algorithm, still processing power is limited. For example, in case only a non-safety critical algorithm is run, the redundant peripheral resources of the other processor core are not available to the processor core connected to the bridging devices.